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Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
DESCRIPTION
The 87L51FA and 87L51FB Single-Chip 3.0V 8-Bit Microcontrollers are manufactured in an advanced CMOS process and are derivatives of the 80C51 microcontroller family. The 87L51FA/B has the same instruction set as the 80C51. This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The 87L51FA contains 8k x 8 memory and the 87L51FB contains 16K x 8 memory, a volatile 256 x 8 read/write data memory, four 8-bit I/O ports, three 16-bit timer/event counters, a Programmable Counter Array (PCA), a multi-source, two-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 87L51FA/B can be expanded using standard 3.3V TTL compatible memories and logic. Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications.
PIN CONFIGURATIONS
T2/P1.0 1 T2EX/P1.1 2 ECI/P1.2 3 CEX0/P1.3 4 CEX1/P1.4 5 CEX2/P1.5 6 CEX3/P1.6 7 CEX4/P1.7 8 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 DUAL IN-LINE PACKAGE 40 VCC 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA/VPP 30 ALE/PROG 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8
FEATURES
WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20
* 80C51 central processing unit * 3.0 to 4.5V VCC range * 8k x 8 EPROM (87L51FA)
16k x 8 EPROM (87L51FB) - Expandable externally to 64k bytes - Quick Pulse programming algorithm - Two level program security system
SU00021
* 256 x 8 RAM, expandable externally to 64k bytes * Three 16-bit timer/counters
- T2 is an up/down counter
* Programmable Counter Array (PCA)
- High speed output - Capture/compare - Pulse Width Modulator - Watchdog Timer
* Four 8-bit I/O ports * Full-duplex enhanced UART
- Framing error detection - Automatic address recognition
* Power control modes
- Idle mode - Power-down mode
* Once (On Circuit Emulation) Mode * Five package styles * OTP package available
1996 Aug 16
3-150
853-1729 17200
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
ORDERING INFORMATION
8k x 8 ROM1 S83L51FA-4N40 6k x 8 ROM1 S83L51FB-4N40 8k x 8 EPROM2 S87L51FA-4N40 16k x 8 EPROM2 S87L51FB-4N40 OTP TEMPERATURE RANGE C AND PACKAGE 0 to +70, 40-Pin Plastic Dual In-line Package 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window 0 to +70, 44-Pin Plastic Leaded Chip Carrier 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 0 to +70, 44-Pin Plastic Quad Flat Pack -40 to +85, 40-Pin Plastic Dual In-line Package -40 to +85, 40-Pin Ceramic Dual In-line Package w/Window -40 to +85, 44-Pin Plastic Leaded Chip Carrier -40 to +85, 44-Pin Plastic Quad Flat Pack 0 to +70, 40-Pin Plastic Dual In-line Package 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window 0 to +70, 44-Pin Plastic Leaded Chip Carrier 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window -40 to +85, 40-Pin Plastic Dual In-line Package -40 to +85, 40-Pin Ceramic Dual In-line Package w/Window -40 to +85, 44-Pin Plastic Leaded Chip Carrier FREQ. (MHz) 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 20 3.5 to 20 3.5 to 20 3.5 to 20 3.5 to 20 3.5 to 20 3.5 to 20 DWG. # SOT129-1
S87L51FA-4F40
S87L51FB-4F40
UV
0590B
S83L51FA-4A44
S83L51FB-4A44
S87L51FA-4A44
S87L51FB-4A44
OTP
SOT187-2
S87L51FA-4K44
S87L51FB-4K44
UV
1472A
S83L51FA-4B44
S83L51FB-4B44
S87L51FA-4B44
S87L51FB-4B44
OTP
SOT307-2
S83L51FA-5N40
S83L51FB-5N40
S87L51FA-5N40
S87L51FB-5N40
OTP
SOT129-1
S87L51FA-5F40
S87L51FB-5F40
UV
0590B
S87L51FA-5A44
S87L51FB-5A44
S87L51FA-5A44
S87L51FB-5A44
OTP
SOT187-2
S83L51FA-5B44
S83L51FB-5B44
S87L51FA-5B44
S87L51FB-5B44
OTP
SOT307-2
S83L51FA-7N40
S83L51FB-7N40
S87L51FA-7N40
S87L51FB-7N40
OTP
SOT129-1
S87L51FA-7F40
S87L51FB-7F40
UV
0590B
S83L51FA-7A44
S83L51FB-7A44
S87L51FA-7A44
S87L51FB-7A44
OTP
SOT187-2
S87L51FA-7K44
S87L51FB-7K44
UV
1472A
S83L51FA-8N40
S83L51FB-8N40
S87L51FA-8N40
S87L51FB-8N40
OTP
SOT129-1
S87L51FA-8F40
S87L51FB-8F40
UV
0590B
S83L51FA-8A44
S83L51FB-8A44
S87L51FA-8A44
S87L51FB-8A44
OTP
SOT187-2
NOTES: 1. Contact Philips for information on low voltage Mask-ROM versions. The 83C51FA and 83C51FB are specified for 2.7V-5.5V operation @ 16MHz. 2. OTP = One Time Programmable EPROM. UV = Erasable EPROM.
1996 Aug 16
3-151
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 2 LATCH
ROM/EPROM
B REGISTER
ACC
STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
ALU SFRs TIMERS PSW P.C.A
BUFFER
PC INCREMENTER
PROGRAM COUNTER PSEN ALE/PROG EA/VPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER
DPTR
PORT 1 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT 3 DRIVERS
P3.0-P3.7
SU00022
1996 Aug 16
3-152
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6 1 40
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44 34
7
39 1 LCC PQFP 33
17
29
11
23
18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1 P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
28 12 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5/CEX2 P1.6/CEX3 P1.7/CEX4 RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7 22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NC* P1.0/T2 P1.1/T2EX P1.2/ECI P1.3/CEX0 P1.4/CEX1
* DO NOT CONNECT
SU00023
* DO NOT CONNECT
SU00024
PIN DESCRIPTIONS
PIN NUMBER MNEMONIC VSS VCC P0.0-0.7 DIP 20 40 39-32 LCC 22 44 43-36 QFP 16 38 37-30 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and receives code bytes during EPROM programming. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions include: T2 (P1.0): Timer/Counter 2 external count input/Clockout T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control ECI (P1.2): External Clock Input to the PCA CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification.
P1.0-P1.7
1-8
2-9
40-44, 1-3
I/O
1 2 3 4 5 6 7 8 P2.0-P2.7 21-28
2 3 4 5 6 7 8 9 24-31
40 41 42 43 44 1 2 3 18-25
I I I I/O I/O I/O I/O I/O I/O
1996 Aug 16
3-153
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
PIN DESCRIPTIONS (Continued)
PIN NUMBER MNEMONIC P3.0-P3.7 DIP 10-17 LCC 11, 13-19 QFP 5, 7-13 TYPE I/O NAME AND FUNCTION Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. Program Store Enable: The read strobe to external program memory. When the 87L51FA/FB is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 1FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 1FFFH. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.
10 11 12 13 14 15 16 17 RST 9
11 13 14 15 16 17 18 19 10
5 7 8 9 10 11 12 13 4
I O I I I I O O I
ALE/PROG
30
33
27
I/O
PSEN
29
32
26
O
EA/VPP
31
35
29
I
XTAL1 XTAL2
19 18
21 20
15 14
I O
NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS - 0.5V, respectively.
TIMER 2
This is a 16-bit up or down counter, which can be operated as either a timer or event counter. It can be operated in one of three different modes (autoreload, capture or as the baud rate generator for the UART). In the autoreload mode the Timer can be set to count up or down by setting or clearing the bit DCEN in the T2CON Special Function Register. The SFR's RCAP2H and RCAP2L are used to reload the Timer upon overflow or a 1-to-0 transition on the T2EX input (P1.1). In the Capture mode Timer 2 can either set TF2 and generate an interrupt or capture its value. To capture Timer 2 in response to a 1-to-0 transition on the T2EX input, the EXEN2 bit in the T2CON must be set. Timer 2 is then captured in SFR's RCAP2H and RCAP2L. As the baud rate generator, Timer 2 is selected by setting TCLK and/or RCLK in T2CON. As the baud rate generator Timer 2 is incremented at 1/2 the oscillator frequency.
ENHANCED UART
The 87L51FA/FB UART has all of the capabilities of the standard 80C51 UART plus Framing Error Detection and Automatic Address Recognition. As in the 80C51, all four modes of operation are supported as well as the 9th bit in modes 2 and 3 that can be used to facilitate multiprocessor communication. The Framing Error Detection allows the UART to look for missing stop bits. If a Stop bit is missing, the FE bit in the SCON SFR is set. The FE bit can be checked after each transmission to detect communication errors. The FE bit can only be cleared by software and is not affected by a valid stop bit. Automatic Address Recognition is used to reduce the CPU service time for the serial port. The CPU only needs to service the UART when it is addressed and, with this done by the on-chip circuitry, the need for software overhead is greatly reduced. This mode works similar to the 9-bit communication mode, except that it uses only 8 bits and the Stop bit is used to cause the RI bit to be set. There are two SFRs associated with this mode. They are SADDR, which holds the slave address and SADEN, which contains a mask that allows selective masking of the slave address so that broadcast addresses can be used.
1996 Aug 16
3-154
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
PROGRAMMABLE COUNTER ARRAY
The PCA is a sophisticated free-running 16 bit Timer/Counter that drives 5 modules that can be individually configured as Capture inputs, software timers, high speed outputs, or pulse width modulated outputs. In addition, module 4 can be configured as a software controlled watchdog timer. The Timer portion of the PCA can be configured to run in one of four different modes. The modes are: 1/2 the oscillator frequency, 1/4 the oscillator frequency, Timer 0 overflows, or from the ECI input. For the Capture/Compare mode each of the modules has a pair of registers associated with it called CCAPnH and CCAPnL (where n = 0, 1, 2, 3, 4 depending on the module). Both positive and negative transitions can be captured. This means that the PCA has the flexibility to measure phase differences, duty cycles, pulse widths and a wide variety of other digital pulse characteristics. In the 16-bit software timer mode each of the modules can generate an interrupt upon a compare. For applications that require accurate pulse widths and edges the PCA modules can be used as High Speed Outputs (HSO). The PCA toggles the appropriate CEXn pin when there is a match between the PCA timer and the modules compare registers. The pulse width modulator mode for the PCA allows the conversion of digital information into analog signals. Each of the 5 modules can be used in this mode. The frequency of the PWM depends on the clock source for the PCA. The 8-bit PWM output is generated by comparing the low byte of the PCA (CL) with the module's CCAPnL SFR. When CL < CCAPnL, the output is high. When CL > CCAPnL, the output is low.
Idle Mode
In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
Power-Down Mode
To save even more power, a Power Down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated. On the 87L51FA/FB either a hardware reset or external interrupt can use an exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
POWER OFF FLAG
The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the 87L51FA/FB rises from 0 to 3.3V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 2.0V for the POF to remain unaffected by the VCC level.
Design Consideration
* When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
ONCETM Mode
The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems using the 87L51FA/FB without the 87L51FA/FB having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87L51FA/FB is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Reset
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up.
1996 Aug 16
3-155
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
Table 1. External Pin Status During Idle and Power-Down Mode
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING 0 to +70 or -40 to +85 -65 to +150 0 to +13.0 -0.5 to +6.5 15 1.5 UNIT C C V V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. Electrical Deviations from Commercial Specifications for Extended Temperature Range DC and AC parameters not included here are the same as in the commercial temperature range table.
1996 Aug 16
3-156
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
DC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C, -40 to +85C, VCC = 3.0V to 4.5V, VSS = 0V TEST SYMBOL VIL VIL1 VIH VIH1 VOL VOL1 VOH VOH1 IIL ITL ILI ICC PARAMETER Input low voltage, except EA2,3 CONDITIONS MIN -0.5 0 2.0 0.7VCC IOL = IOL = 1.6mA6 3.2mA6 VCC - 0.5 VCC - 0.7 -50 -650 10 9 2 10 40 22 6 75 225 15 LIMITS TYP1 MAX 0.8 0.8 VCC+0.5 VCC+0.5 0.45 0.45 UNIT V V V V V V V V A A A mA mA A k pF
Input low voltage to EA2,3 Input high voltage, except XTAL1, RST2,4 Input high voltage, XTAL1, RST2,4 Output low voltage, ports 1, 2, 35 PSEN5 PSEN7
Output low voltage, port 0, ALE,
Output high voltage, ports 1, 2, 3, ALE,
IOH = -20A IOH = -3.2mA VIN = 0.4V See note 9 0.45 VIN < VCC - 0.3 See note 11
Output high voltage (port 0 in external bus mode), ALE8, PSEN7 Logical 0 input current, ports 1, 2, 32 Logical 1-to-0 transition current, ports 1, 2, 32 Input leakage current, port 0 Power supply current:2 Active mode @ 20MHz10 Idle mode @ 20MHz Power-down mode Internal reset pull-down resistor Pin capacitance12 (except EA)
RRST CIO
NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 3.3V. 2. These values apply only to Tamb = 0C to +70C. 3. For VCC voltages above 3.6V and less than 5.5V, VIL = 0.3VCC - 0.1 4. For VCC voltages above 3.6V and less than 5.5V, VIH = 0.3VCC + 0.92 5. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA (*NOTE: This is 85C specification.) Maximum IOL per port pin: 26mA Maximum IOL per 8-bit port: 71mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 6. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 7. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 8. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 9. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 1.5V. 10. ICCMAX at other frequencies is given by: Active mode: ICCMAX = 0.8 x FREQ + 6: Idle mode: ICCMAX = 0.19 x FREQ +2.50, where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 8. 11. See Figures 9 through 12 for ICC test conditions. 12. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA is 25pF). These values are guaranteed by design and are not tested.
1996 Aug 16
3-157
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C, -40 to +85C, VCC = 3.0V to 4.5V, VSS = 0V1, 2, 3 16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 4 4 4 4 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 1 492 8 0 12tCLCL 10tCLCL-133 2tCLCL-117 0 s ns ns ns 5 5 5 5 High time Low time Rise time Fall time 12 12 20 20 20 20 20 20 ns ns ns ns 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 3 2, 3 2, 3 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high 23 137 122 13 13 287 0 103 tCLCL-40 0 65 350 397 237 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 0 tCLCL+40 275 275 147 0 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 1 PARAMETER Oscillator frequency -4, -5 -7, -8 1 1 1 1 1 1 1 1 1 1 1 ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 37 207 10 32 142 82 0 tCLCL-25 5tCLCL-105 10 85 22 32 150 tCLCL-30 3tCLCL-45 3tCLCL-105 MIN MAX VARIABLE CLOCK MIN 3.5 3.5 2tCLCL-40 tCLCL-40 tCLCL-30 4tCLCL-100 MAX 16 20 UNIT MHz MHz ns ns ns ns ns ns ns ns ns ns ns
tXHDV 4 Clock rising edge to input data valid 492 10tCLCL-133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 87L51FA/FB to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.
1996 Aug 16
3-158
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL= Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL tLLIV
tPLPH tPLIV tPLAZ tPXIX
INSTR IN
PSEN
tPXIZ
tLLAX
PORT 0 A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00056
Figure 1. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH
SU00025
Figure 2. External Data Memory Read Cycle
1996 Aug 16
3-159
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX tQVWH
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPF
A0-A15 FROM PCH
SU00026
Figure 3. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 4. Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 5. External Clock Drive
1996 Aug 16
3-160
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
VCC-0.3
0.3VCC+0.92 0.3VCC-0.1
0.3V
NOTE: AC inputs during testing are driven at VCC -0.3 for a logic `1' and 0.3V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL for a logic `0'.
SU00051
Figure 6. AC Testing Input/Output
VLOAD+0.1V VLOAD VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00011
Figure 7. Float Waveform
25 Note: 3.3V operation will reduce ICC vs. XTAL frequency. This curve will change as characterization data becomes available. MAX ACTIVE MODE IDDMAX = 0.8 X FREQ. + 6.0
20
15 ICC mA 10 TYP ACTIVE MODE MAX IDLE MODE IDDIDLE = 0.19 X FREQ. + 2.5 TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz 20MHz
5
FREQ AT XTAL1
SU00052
Figure 8. ICC vs. FREQ Valid only within frequency specifications of the device under test
1996 Aug 16
3-161
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC
VCC ICC
VCC
RST
SU00719
SU00720
Figure 9. ICC Test Condition, Active Mode All other pins are disconnected
Figure 10. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 11. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC
SU00016
Figure 12. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 4.5V
1996 Aug 16
3-162
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
EPROM CHARACTERISTICS
The 87L51FA/FB is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87L51FA/FB contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87L51FA/FB manufactured by Philips. Table 2 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 13 and 14. Figure 15 shows the circuit configuration for normal program memory verification.
Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 15. The other pins are held at the `Verify Code Data' levels indicated in Table 2. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = B1H indicates 87L51FA = B2H indicates 87L51FB
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 13. Note that the 87L51FA/FB is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 13. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 2 are held at the `Program Code Data' levels indicated in Table 2. The ALE/PROG is pulsed low from 5 to 25 times as shown in Figure 14. To program the encryption table, repeat the 5 to 25 pulse programming sequence for addresses 0 through 1FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 5 to 25 pulse programming sequence using the `Pgm Security Bit' levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 2, and which satisfies the timing specifications, is suitable.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an opaque label be placed over the window. For elevated temperature or environments where solvents are being used, apply Kapton tape Fluorglas part number 2345-5, or equivalent. The recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15W-s/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000W/cm2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state.
Table 2. EPROM Programming Modes1,2,3
MODE Read signature Program code data Verify code data Pgm encryption table Pgm security bit 1 RST 1 1 1 1 1 PSEN 0 0 0 0 0 ALE/PROG 1 04 1 04 04 EA/VPP 1 VPP 1 VPP VPP P2.7 0 1 0 1 1 P2.6 0 0 0 0 1 P3.7 0 1 1 1 1 P3.6 0 1 1 0 1
Pgm security bit 2 1 0 04 VPP 1 1 0 0 NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75V 0.25V. 3. VCC = 5V10% during programming and verification. 4. ALE/PROG receives 5 to 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100s (10s) and high for a minimum of 10s. TMTrademark phrase of Intel Corporation. 1996 Aug 16 3-163
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87L51FA 87L51FB P0 PGM DATA +12.75V 25 100s PULSES TO GROUND 0 1 0 A8-A13
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.5
SU00053A
Figure 13. Programming Configuration
5 to 25 PULSES 1 ALE/PROG: 0
10s MIN 1 ALE/PROG: 0
100s+10
SU00054
Figure 14. PROG Waveform
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87L51FA 87L51FB P0 PGM DATA 1 1 0 0 ENABLE 0 A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00055A
Figure 15. Program Verification
1996 Aug 16
3-164
Philips Semiconductors
Product specification
CMOS single-chip 3.0V 8-bit microcontrollers
87L51FA/87L51FB
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21C to +27C, VCC = 5V10%, VSS = 0V (See Figure 16) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s PARAMETER MIN 12.5 MAX 13.0 50 6 UNIT V mA MHz
PROGRAMMING* P1.0-P1.7 P2.0-P2.4 ADDRESS
VERIFICATION* ADDRESS
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC 1 EA/VPP LOGIC 0
LOGIC 1
tEHSH
P2.7 ENABLE
tELQV
tEHQZ
SU00020
NOTE: * FOR PROGRAMMING VERIFICATION SEE FIGURE 13.
FOR VERIFICATION CONDITIONS SEE FIGURE 15.
Figure 16. EPROM Programming and Verification
1996 Aug 16
3-165

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